The invention is concerned with the transfer of data from a number of external peripheral modules (e.g., switches) to a memory (e.g., SDRAM) via a DMA (Direct Memory Access) Controller. At a given time, each peripheral module might have one or more data packets to be transferred to the memory via the DMA Controller.
In known arrangements, the data packets to be transferred to the memory via the DMA Controller are queued up in each peripheral module. Assuming there is sufficient memory space, the data packets are transferred sequentially, i.e., the first in the queue followed by the second in the queue and so on. However, there may only be space for certain packet classifications and not others. Thus, if a particular classification data packet is first in the queue for a given peripheral and, if there is no memory space available for the data packet's classification, the data packet cannot be transferred from the peripheral module. Therefore, the data packet will block those data packets that are behind it in the queue. The later data packets may be packets whose classifications do have memory space available, so those packets will be blocked by the earlier packets where memory space is not available and there will be congestion of packets within the peripheral.
Thus, in known arrangements, the peripheral modules often become congested, which prevents smooth operation. Also, certain data packets may be blocked, even when there is sufficient memory space for those data packets.